Fpga Implementation of a Vedic Convolution Algorithm

In digital signal processing convolution is a fundamental computation that is ubiquitous in many application areas. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) methods are employed. In this paper, block convolution process is proposed using a multiplier architecture based on vertical and crosswise algorithm of Ancient Indian Vedic Mathematics and embedding it in OLA method for reducing calculations.And as the vedic multiplier is been used it is named as Vedic convolution algorithm.The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) for the FPGA , as it is being increasingly used for variety of computationally intensive applications.Simulation and synthesis is done using Xilinx.